1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to the formation of oxides in semiconductor fabrication.
2. Description of the Related Art
Semiconductor memory devices, such as dynamic random access memories (DRAM""s) include capacitors accessed by transistors to store data. Deep trench (DT) capacitors are among the types of capacitors used in DRAM technology. Deep trench capacitors are typically buried within a semiconductor substrate.
Referring to FIG. 1, a silicon substrate 10 is shown having a trench 12 etched therein. Typically, substrate 10 is p-doped. To form a buried plate 14, a lower portion of trench 12 has n-type dopants diffused therein. Buried plate 14 is formed by depositing a dopant rich material into the lower portion of trench 12 and heating the material to drive n-type dopants into substrate 10 to form buried plate 14. Buried plate 14 is separated from an n-type doped region 16 (source or drain) of an access transistor 18 by a p-doped substrate region 20 (p-well). Consequently, there exists an n/p/n junction along a vertical side of trench 12. This n/p/n junction forms a transistor. This undesirable transistor is called a vertical device and can cause a severe leakage of charge from buried plate 14 to access transistor 18 if the undesired transistor is turned on.
To prevent the vertical device from being turned on, a thick dielectric layer is needed on top of the n/p/n junction. This layer is called a trench collar 22 which conventionally includes silicon dioxide. Trench collar 22 determines a threshold voltage Vt. Once the applied voltage is larger than Vt the vertical device is turned on and charge flows through the n/p/n junction. The thickness of oxide of collar 22 should be large enough to prevent the vertical device from being turned on during DRAM operation.
Conventionally, voltages in the order of VD/2 are applied to trench 12 where VD is the power supply voltage (typically about 3 volts). To prevent the vertical device from turning on, an oxide thickness of collar 22 above 25 nm is needed. This collar oxide is typically formed by a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) process with a subsequent collar open etch or with a localized oxidation of silicon (LOCOS) process.
The LOCOS process permits for an easier and cheaper process integration flow when compared to the CVD/PVD processes, and LOCOS is more suitable for small groudrules (i.e., better trench profile). However, the conventional LOCOS collar suffers from the following drawbacks:
1. High temperatures up to 1050 degrees C. are required. This significantly contributes to the thermal budget and can cause stress at the trench device interface resulting in dislocation in the substrate. These dislocations cause variable retention time (VRT) problems for the deep trench capacitor.
2. The LOCOS oxide thickness shows a severe dependence on the silicon crystal orientation of the substrate resulting in a non-uniform collar with thin regions. In these regions, Vt drops significantly causing reliability problems.
3. Collar thickness measurement and control are difficult. Thickness measurements are performed on the surface of monitor wafers. These surfaces have different crystal orientations. Therefore, this thickness does not necessarily relate directly to the collar thickness.
4. To prevent oxidation of the whole trench, a nitride liner is required in the bottom portion of the trench where no oxide is to be formed. The conventional LOCOS process includes a liner which is thicker than 5 nm (typically 5.8 nm) to prevent oxidation of the silicon interface of the substrate. This nitride liner is difficult to remove.
Therefore, a need exists for a method for forming a trench collar which does not suffer from the disadvantages of conventional processes. A further need exists for a self-aligning trench collar which can be formed without significant impact to a thermal processing budget.
A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.
In alternate methods, the step of applying a voltage between the wafer and the solution to create the potential difference such that the voltage applied controls the thickness of the oxide may be included. The solution preferably includes water, and the electrolyte preferably includes an ionic compound. The step of placing the wafer in an electrochemical cell may include the steps of placing the wafer in an electrochemical cell such that the wafer has an exposed surface area including the exposed p-doped silicon regions thereon and providing a counter electrode in the solution having a substantially same exposed surface area as the exposed surface area of the wafer. The step of placing the wafer in an electrochemical cell may include the step of sealing other than exposed areas of the wafer to prevent contact with the solution. The step of placing the wafer in an electrochemical cell may alternately include the step of placing the wafer in an electrochemical cell such that a front surface of the wafer including the exposed p-doped silicon regions is exposed to an oxidation chamber and a back surface of the wafer is exposed to a second solution which transfers a potential to the wafer to cause the potential difference. The solution including electrolytes preferably interacts with the p-doped silicon regions by reacting according to the reaction:
Si+H2Oxe2x86x92SiO2+4H++4exe2x88x92.
The reaction preferably occurs at about room temperature. A semiconductor device may be fabricated according to the above methods.
A method for electrochemically forming a trench collar includes the steps of forming a deep trench in a silicon substrate, the deep trench having sidewalls adjacent to a p-doped well formed in the substrate and a buried plate formed within the substrate surrounding a lower portion of the deep trench, placing the silicon substrate in an electrochemical cell, the electrochemical cell including a solution having electrolytes dissolved therein and applying a first potential to the silicon substrate and a second potential to the solution to form a potential difference therebetween such that a trench collar is electrochemically formed on the sidewalls of the deep trench adjacent to the p-doped well and selective to the buried plate.
Another method for electrochemically forming a trench collar includes the steps of forming a deep trench in a silicon substrate, the deep trench having sidewalls adjacent to a p-doped well formed in the substrate and a buried plate formed within the substrate surrounding a lower portion of the deep trench, placing the silicon substrate in an electrochemical cell, the electrochemical cell including an aqueous solution having electrolytes dissolved therein, applying a first potential to the silicon substrate and a second potential to the solution to form a potential difference therebetween, reacting the aqueous solution with the p-doped well formed in the substrate to form an electrochemically formed trench collar on the sidewalls of the deep trench adjacent to the p-doped well and selective to the buried plate and adjusting a thickness of the trench collar by adjusting the potential difference.
In alternate methods, the potential difference is preferably applied to control the thickness of the trench collar. The solution preferably includes water, and the electrolyte preferably includes an ionic compound. The step of placing the silicon substrate in an electrochemical cell may include the steps of placing the silicon substrate in an electrochemical cell such that the substrate has an exposed surface area including the sidewalls of the deep trench adjacent to the p-doped well and providing a counter electrode in the solution having a substantially same exposed surface area as the exposed surface area of the substrate. The step of placing the silicon substrate in an electrochemical cell may include the step of sealing other than exposed areas of the substrate to prevent contact with the solution. The step of placing the silicon substrate in an electrochemical cell may include the step of placing the silicon substrate in an electrochemical cell such that a front surface of the substrate including the sidewalls of the deep trench adjacent to the p-doped well is exposed to an oxidation chamber and a back surface of the wafer is exposed to a second solution which transfers the first potential to the substrate to cause the potential difference. The solution including electrolytes preferably interacts with the sidewalls of the deep trench adjacent to the p-doped well by reacting according to the reaction:
Si+H2Oxe2x86x92SiO2+4H++4exe2x88x92.
The reaction preferably occurs at about room temperature. The method may include the step of annealing the trench collar to densify the trench collar. A semiconductor device may be fabricated according to the above methods.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.